1. Field of the Invention
The present invention generally relates to computer-aided design, and particularly relates to the designing of a semiconductor integrated circuit taking into account process variation.
2. Description of the Related Art
Variation that needs to be taken into account at the time of the operation of a semiconductor integrated circuit includes not only a process variation that is a variation in the characteristics of the semiconductor integrated circuit but also a power-supply-voltage variation and a temperature variation that are variations in the operating environment. In the designing of a semiconductor integrated circuit, timing check and layout modification are repeated as many time as necessary to provide a circuit design that does not have a timing failure. In such timing check, the power-supply-voltage variation, temperature variation, and process variation are all required to be taken into account.
To be specific, under the conditions that bring about a maximum delay within the tolerable power-supply-voltage range and the tolerable temperature range, a maximum-delay condition that further achieves a maximum delay time due to process variation is taken into account, and, also, under the conditions that bring about a minimum delay within the tolerable power-supply-voltage range and the tolerable temperature range, a minimum-delay condition that further achieves a minimum delay time due to process variation is taken into account, A check is then made as to whether both the delay time of the minimum-delay condition and the delay time of the maximum-delay condition satisfy predetermined delay time requirements. If the check finds that these requirements are not satisfied, the layout is modified through cell insertion, cell removal, cell replacement, cell displacement, and/or interconnection modification so as to resolve the error.
FIG. 1 is a flowchart showing a procedure from the designing of a semiconductor integrated circuit to the operating of the semiconductor integrated circuit after implementation.
At step S1, power-supply-voltage/temperature ranges are determined. The power-supply-voltage/temperature ranges are system-dependent, and are determined by a party that designs the system. At step S2, manufacturing process variation is determined. The manufacturing process variation is a range of process variation that is determined in advance by taking into account how much variation is expected during the manufacturing of the semiconductor integrated circuit, and is determined by a semiconductor vendor (i.e., the party that manufactures and provides the semiconductor integrated circuit).
At step S3, all the possible variations are computed. At step S4, libraries designed to cover all the ranges of variations are generated. These libraries define the cell size, gate-input capacitance, output-drive capability, delay time, and the like of each cell. With respect to each of the gate-input capacitance, the output-drive capability, the delay time, and the like, a maximum value and minimum value are defined by taking into account all the variations inclusive of the power-supply-voltage/temperature ranges and the manufacturing process variation.
At step S5, physical designing and manufacturing are performed. Namely, timing checks are performed by considering the variations by use of the libraries, thereby determining a physical layout, based on which the semiconductor integrated circuit is manufactured.
At step S6, a process is measured by use of a process monitor in the manufacturing test. A special circuit called “process monitor” is embedded at a predetermined position on the wafer. The characteristics of this circuit are checked to measure the process of the manufactured semiconductor integrated circuit. If the manufactured semiconductor integrated circuit has a manufacturing process that falls within the expected range, the circuit is treated as a proper product. If the process is not within the expected range of the manufacturing process variation, the circuit is rejected as unusable.
At step S7, the semiconductor integrated circuit is operated within the power-supply-voltage/temperature ranges that are determined at the beginning.
As the development of the semiconductor technology serves to further miniaturize semiconductor integrated circuits, the process variation of semiconductor integrated circuits tends to increase. When a total variation that includes a process variation, a power supply voltage variation, and a temperature variation is taken into consideration, the maximum delay of signal propagation in a semiconductor integrated circuit may possibly be several-times larger than the minimum delay. A current designing process first sets a tolerable power supply voltage range and tolerable temperature range, and the upper end and lower end of a total variation are derived by taking into account process variation in addition to these tolerable ranges, followed by designing a circuit that properly operates under all the conditions that fall within the derived range of variation. In order to design a semiconductor integrated circuit that properly operates in a such a large variation range in which the maximum delay may be several-times larger than the minimum delay, the designing process of a semiconductor integrated circuit becomes complex, and, also, the number of process steps increases, resulting in an increased amount of time and labor.
[Patent Document 1] Japanese Patent Application Publication No. 2002-353083
[Patent Document 2] Japanese Patent Application Publication No. 2002-324097
Accordingly, there is a need for a method of designing a semiconductor integrated circuit that can finish designing in a short time.